37.13.22 ADCCNTB – ADC Sample Count Base Address Register

Name:	ADCCNTB
Offset:	0x320
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	ADCCNTB[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	ADCCNTB[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ADCCNTB[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ADCCNTB[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – ADCCNTB[31:0] Analog-to-Digital Count Base Address bits

The ADCCNTB register contains the user-defined RAM address at which the DMA engine will start saving the current count of output samples (if the DMACNTEN bit (ADCDMASTAT[15]) is set), which is already written to each of the buffers in the System RAM for each ADC core. The ADCx core will have its Buffer A current sample count saved at the address ((ADCCNTB) + (2 × x)) and its Buffer B current sample count saved at the address ((ADCCNTB) + (2 × (x + 1))). Where ‘x’ is the dedicated ADC core ID.