37.13.21 ADCDMASTAT – ADC DMA Status Register
| Name: | ADCDMASTAT |
| Offset: | 0x310 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DMAGEN | RBF_IEN0 | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WR_OVF_ERR | RBF0 | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DMA_CNT_EN | RAF_IEN0 | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RAF0 | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 31 – DMAGEN DMA Global Enable bit
Bit 24 – RBF_IEN0 RAM Buffer B Full Interrupt Enable bit
| Value | Description |
|---|---|
| 1 |
Interrupts are enabled and generated when the RBFx Status bit is set |
| 0 |
Interrupts are disabled |
Bit 23 – WR_OVF_ERR DMA Write Overflow Error bit
Note: This bit is cleared by hardware after a software read of the
ADCDMASTAT register.
| Value | Description |
|---|---|
| 1 |
DMA write overflow error has occurred (circular buffer) |
| 0 |
DMA write overflow error has not occurred |
Bit 16 – RBF0 RAM Buffer B Full Status bit
Note: These bits are self-clearing upon being a read by software.
| Value | Description |
|---|---|
| 1 |
RAM Buffer B is full |
| 0 |
RAM Buffer B is not full |
Bit 15 – DMA_CNT_EN DMA Write Overflow Error bit
Note: This bit is cleared by hardware after a software read of the
ADCDMASTAT register.
| Value | Description |
|---|---|
| 1 |
DMA write overflow error has occurred (circular buffer) |
| 0 |
DMA write overflow error has not occurred |
Bit 8 – RAF_IEN0 RAM Buffer A Full Interrupt Enable bit
| Value | Description |
|---|---|
| 1 |
Interrupts are enabled and generated when the RAFx status bit is set |
| 0 |
Interrupts are disabled |
Bit 0 – RAF0 RAM Buffer A Full Status bit
Note: These bits are self-clearing upon being a read by software.
| Value | Description |
|---|---|
| 1 |
RAM Buffer A is full |
| 0 |
RAM Buffer A is not full |