37.13.25 ADC Timing for First Class Channel Register (x = 0)
| Name: | ADC0TIME |
| Offset: | 0x350 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| EISx[2:0] | SELRESx[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| BCHENx | ADCDIVx[6:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SAMCx[9:8] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SAMCx[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 28:26 – EISx[2:0] Early Interrupt Select Bits for First Class Channel index x (x=0)
Note: Depending on the bit resolution selection field
SELRESx[1:0], the allowed EISx[2:0] values are:
- For SELRESx[1:0] ==
2’b11, i.e. 12-bit Resolution, all 8 possible settings for Early interrupt are allowed, 0 to 7 (1 to 8 Core Clock periods early) - For SELRESx[1:0] ==
2’b10, i.e. 10-bit Resolution, all 8 possible settings for Early interrupt are allowed, 0 to 7 (1 to 8 Core Clock periods early) - For SELRESx[1:0] ==
2’b01, i.e. 8-bit Resolution, only the 6 lowest settings are allowed, 0 to 5 (1 to 6 Core Clock periods early) - For SELRESx[1:0] ==
2’b00, i.e. 6-bit Resolution, only the 4 lowest settings are allowed, 0 to 3 (1 to 4 Core Clock periods early)
The hardware will utilize the maximum allowed Early Interrupt setting if the user programs the EISx bit-field to a nonallowed value.
| Value | Description |
|---|---|
| 111 | The early ready interrupt is generated 8 ADC core clocks prior to end of conversion |
| 110 | The early ready interrupt is generated 7 ADC core clocks prior to end of conversion |
| 101 | The early ready interrupt is generated 6 ADC core clocks prior to end of conversion |
| 100 | The early ready interrupt is generated 5 ADC core clocks prior to end of conversion |
| 011 | The early ready interrupt is generated 4 ADC core clocks prior to end of conversion |
| 010 | The early ready interrupt is generated 3 ADC core clocks prior to end of conversion |
| 001 | The early ready interrupt is generated 2 ADC core clocks prior to end of conversion |
| 000 | The early ready interrupt is generated 1 ADC core clock prior to end of conversion |
Bits 25:24 – SELRESx[1:0] ADCx Resolution Select bits
00 -> 6 bits / 01 -> 8 bits / 10 -> 10 bits / 11 -> 12 bits
| Value | Description |
|---|---|
| 00 | Sets the resolution to 6 bits for the ADC |
| 01 | Sets the resolution to 8 bits for the ADC |
| 10 | Sets the resolution to 10 bits for the ADC |
| 11 | Sets the resolution to 12 bits for the ADC |
Bit 23 – BCHENx Buffer Channel Enable bit
Bits 22:16 – ADCDIVx[6:0] ADCx Clock Divisor bits
Division Ratio for the SAR ADC core clock core_clk[x] of the First Class Channel index x (x=0) from the ADC control clock ctl_clk.
The ADCDIVx bit field divides the ADC control clock ctl_clk with period TQ:
| Value | Description |
|---|---|
| 1111111 | 2TQ·(ADCDIVx[6:0]) = 254·TQ = TADx |
| ······ | |
| 0000011 | 2TQ·(ADCDIVx[6:0]) = 6·TQ = TADx |
| 0000010 | 2TQ·(ADCDIVx[6:0]) = 4·TQ = TADx |
| 0000001 | 2TQ·(ADCDIVx[6:0]) = 2·TQ = TADx |
| 0000000 | Reserved (but still implemented as 2TQ·(ADCDIVx[6:0]) = 2·TQ = TADx) |
Bits 9:0 – SAMCx[9:0] ADCx Sample Time bits
This bit field uses the encoding as follows:
SAMCx[9:0] is specified in TADX = period of the core_clk[x], which is the ADC core clock for the first class ADC core index x, controlled by ADCDIVx[6:0] defined above in this table.
| Value | Description |
|---|---|
| 1111111111 | 1025 TADX |
| ····· | |
| 0000000001 | 3 TADX |
| 0000000000 | 2 TADX |