37.13.4 ADCTRGMODE - ADC Triggering Mode for Dedicated ADC Register
Name: | ADCTRGMODE |
Offset: | 0x30 |
Reset: | 0x00000000 |
Property: | - |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
SH0ALT[1:0] | |||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
STRGEN0 | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SSAMPEN0 | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bits 17:16 – SH0ALT[1:0] ADC0 Analog Input Select bit
Value | Description |
---|---|
11 |
Reserved |
10 |
ANB0 |
01 | ANA0 |
00 | AN0 |
Bit 8 – STRGEN0 ADC0 Presynchronized Triggers bit
Value | Description |
---|---|
1 |
ADC0 uses presynchronized triggers |
0 |
ADC0 does not use presynchronized triggers |
Bit 0 – SSAMPEN0 ADC0 Synchronous Sampling bit
Value | Description |
---|---|
1 |
ADC0 uses synchronous sampling for the first sample after being idle or disabled |
0 | ADC0 does not use synchronous sampling |