37.13.4 ADCTRGMODE - ADC Triggering Mode for Dedicated ADC Register

Name: ADCTRGMODE
Offset: 0x30
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
       SH0ALT[1:0] 
Access R/WR/W 
Reset 00 
Bit 15141312111098 
        STRGEN0 
Access R/W 
Reset 0 
Bit 76543210 
        SSAMPEN0 
Access R/W 
Reset 0 

Bits 17:16 – SH0ALT[1:0] ADC0 Analog Input Select bit

ValueDescription
11

Reserved

10

ANB0

01 ANA0
00 AN0

Bit 8 – STRGEN0 ADC0 Presynchronized Triggers bit

ValueDescription
1

ADC0 uses presynchronized triggers

0

ADC0 does not use presynchronized triggers

Bit 0 – SSAMPEN0 ADC0 Synchronous Sampling bit

ValueDescription
1

ADC0 uses synchronous sampling for the first sample after being idle or disabled

0 ADC0 does not use synchronous sampling