37.13.2 ADCCON2 – ADC Control Register 2

This register controls the reference selection for the ADC core, the sample time for the shared ADC core, interrupt enable for reference, early interrupt selection and clock division selection for the shared ADC.

Name:	ADCCON2
Offset:	0x10
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24
	BGVRRDY	REFFLT	EOSRDY	CVD_CPL[2:0]			SAMC[9:8]
Access	R/HS/HC	R/HS/HC	R/HS/HC	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	SAMC[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	BGVRIEN	REFFLTIEN	EOSIEN			ADCEIS[2:0]
Access	R/W	R/W	R/W			R/W	R/W	R/W
Reset	0	0	0			0	0	0


Bit	7	6	5	4	3	2	1	0
		ADCDIV[6:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0

Bit 31 – BGVRRDY Band Gap Voltage/ADC Reference Voltage Status bit

Data processing is valid only after BGVRRDY is set by hardware, so the application code must check that the BGVRRDY bit is set to ensure data validity. This bit set to ‘0’ when ON (ADCCON1[15]) = 0.

Value	Description
0	Either or both band gap voltage and ADC reference voltages (V_REF) are not ready
1	Both band gap voltage and ADC reference voltages (V_REF) are ready

Bit 30 – REFFLT Band Gap/V_REF/A_VDD BOR Fault Status bit

This bit is cleared when the ON bit (ADCCON1[15]) = 0 and the BGVRRDY bit = 1.

Value	Description
0	Band gap and V_REF voltage are working properly
1	Fault in band gap or the V_REF voltage while the ON bit (ADCCON1[15]) was set. Most likely a band gap or V_REF fault is caused by a BOR of the analog V_DD supply.

Bit 29 – EOSRDY End of Scan Interrupt Status bit

This bit is cleared when ADCCON2[31:24] are read in software.

Value	Description
0	Scanning is not complete
1	All analog inputs configured for scanning through the scan trigger (all analog inputs specified in the ADCCSS1 register) complete their conversions.

Bits 28:26 – CVD_CPL[2:0] CVD Partly Line Capacitor Setting; Cpline = CVD_CPL[2:0] × 2.5 pF = 0–17.5 pF

Bits 25:16 – SAMC[9:0] Sample Time for the Shared ADC bits

Where T_AD7 = Period of the ADC conversion clock for the Shared ADC controlled by the ADCCON2.ADCDIV[6:0] bits

Value	Description
0x3ff	1025 T_AD7
...	—
0x001	3 T_AD7
0x000	2 T_AD7

Bit 15 – BGVRIEN Band Gap/V_REF Voltage Ready Interrupt Enable bit

Value	Description
0	No interrupt is generated when the BGVRRDY bit is set
1	Interrupt is generated when the BGVRDDY bit is set

Bit 14 – REFFLTIEN Band Gap/V_REF Voltage Fault Interrupt Enable bit

Value	Description
0	No interrupt is generated when the REFFLT bit is set
1	Interrupt is generated when the REFFLT bit is set

Bit 13 – EOSIEN End of Scan Interrupt Enable bit

Value	Description
0	No interrupt is generated when the EOSRDY bit is set
1	Interrupt is generated when the EOSRDY bit is set

Bits 10:8 – ADCEIS[2:0] Early Interrupt Select bits

These early interrupt select bits are for the Shared ADC Core; applies to all shared channels.

These bits select the number of clocks prior to the arrival of valid data that the associated interrupt is generated.

The hardware will utilize the maximum allowed early interrupt setting if the user programs the ADCEIS bit-field to a non-allowed value.

Value	Description
111	The early ready interrupt is generated 8 ADC core clocks prior to end of conversion.
110	The early ready interrupt is generated 7 ADC core clocks prior to end of conversion.
101	The early ready interrupt is generated 6 ADC core clocks prior to end of conversion.
100	The early ready interrupt is generated 5 ADC core clocks prior to end of conversion.
011	The early ready interrupt is generated 4 ADC core clocks prior to end of conversion.
010	The early ready interrupt is generated 3 ADC core clocks prior to end of conversion.
001	The early ready interrupt is generated 2 ADC core clocks prior to end of conversion.
000	The early ready interrupt is generated 1 ADC core clocks prior to end of conversion.

Bits 6:0 – ADCDIV[6:0] Division Ratio for the Shared SAR ADC Core Clock bits

The ADCDIV[6:0] bits divide the ADC control clock (T_Q) to generate the clock for the shared SAR ADC.

Value	Description
1111111	254 * T_Q = T_AD7
...	—
0000011	6 * T_Q = T_AD7
0000010	4 * T_Q = T_AD7
0000001	2 * T_Q = T_AD7
0000000	Reserved