38.7.3 CVD Status Register
| Name: | CVDSTAT |
| Offset: | 0x08 |
| Reset: | 0x20000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FIFOFULL | FIFOWM | FIFOMT | FIFOCNT[9:8] | ||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 1 | 0 | 0 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FIFOCNT[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SD4INT | SD4DONE | SD4BUSY | SD3INT | SD3DONE | SD3BUSY | ||||
| Access | R/W/HS | R | R | R/W/HS | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SD2INT | SD2DONE | SD2BUSY | SD1INT | SD1DONE | SD1BUSY | ||||
| Access | R/W/HS | R | R | R/W/HS | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – FIFOFULL Results FIFO is Full
| Value | Description |
|---|---|
| 1 | FIFO is full |
| 0 | Not full |
Bit 30 – FIFOWM
| Value | Description |
|---|---|
| 1 | FIFO reached the programmed FIFOTHRESH threshold |
| 0 | FIFO did not reach the programmed FIFOTHRESH threshold |
Bit 29 – FIFOMT
| Value | Description |
|---|---|
| 1 | FIFO is empty |
| 0 | FIFO is not empty |
Bits 25:16 – FIFOCNT[9:0]
Bit 14 – SD4INT
| Value | Description |
|---|---|
| 1 | Scan Descriptor 4 caused an interrupt |
| 0 | Scan Descriptor 4 did not cause an interrupt |
Bit 13 – SD4DONE
Note: The hardware clears this bit upon receiving next trigger
for Scan Descriptor 4.
| Value | Description |
|---|---|
| 1 | Scan Descriptor 4 completed at least once |
| 0 | Scan Descriptor 4 did not complete |
Bit 12 – SD4BUSY
| Value | Description |
|---|---|
| 1 | Scan Descriptor 4 is in progress |
| 0 | Scan Descriptor 4 is not in progress |
Bit 10 – SD3INT
| Value | Description |
|---|---|
| 1 | Scan Descriptor 3 caused an interrupt |
| 0 | Scan Descriptor 3 did not cause an interrupt |
Bit 9 – SD3DONE
Bit 8 – SD3BUSY
| Value | Description |
|---|---|
| 1 | Scan Descriptor 3 is in progress |
| 0 | Scan Descriptor 3 is not in progress |
Bit 6 – SD2INT
| Value | Description |
|---|---|
| 1 | Scan Descriptor 2 caused an interrupt |
| 0 | Scan Descriptor 2 did not cause an interrupt |
Bit 5 – SD2DONE The controller sets this bit if Scan Descriptor 2 completes at least once. Core clears this bit upon receiving next trigger for Scan Descriptor 2.
Bit 4 – SD2BUSY
| Value | Description |
|---|---|
| 1 | Scan Descriptor 2 caused an interrupt |
| 0 | Scan Descriptor 2 did not cause an interrupt |
Bit 2 – SD1INT Scan Descriptor 1 caused an interrupt
| Value | Description |
|---|---|
| 1 | Scan Descriptor 1 caused an interrupt |
| 0 | Scan Descriptor 1 did not cause an interrupt |
Bit 1 – SD1DONE The controller sets this bit if Scan Descriptor 1 completed at least once. Core clears this bit upon receiving next trigger for Scan Descriptor 1.
Bit 0 – SD1BUSY Scan Descriptor 1 is in progress
| Value | Description |
|---|---|
| 1 | Scan Descriptor 1 is in progress |
| 0 | Scan Descriptor 1 is not in progress |