38.7.2 CVD ADC Configuration Register

Name:	CVDADC
Offset:	0x04
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
					ADCCON	ADCCON	ADCCON[1:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
					ADCCON	ADCCON[2:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bit 11 – ADCCON ANN1 Channel Enabled

Bit 10 – ADCCON Shared SARCORE Differential Enabled

Bits 9:8 – ADCCON[1:0] Shared SARCORE Resolution Select

Bit 3 – ADCCON CVD Enabled

Bits 2:0 – ADCCON[2:0] ADCON2.CVD_CPL[2:0] Register Field

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