26.8.10 CLCxGLS3

CLCx Gate4 Logic Select Register
Name: CLCxGLS3
Address: 0xE30,0xE3A,0xE44,0xE4E,0xE58,0xE62,0xE6C,0xE76

Bit 76543210 
 G4D4TG4D4NG4D3TG4D3NG4D2TG4D2NG4D1TG4D1N 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset xxxxxxxx 

Bits 1, 3, 5, 7 – G4DyT

dyT: Gate4 Data ‘y’ True (non-inverted) bit
Reset States: 
Default = xxxx
POR/BOR = x
All Other Resets = u
ValueDescription
1 dyT is gated into g4
0 dyT is not gated into g4

Bits 0, 2, 4, 6 – G4DyN

dyN: Gate4 Data ‘y’ Negated (inverted) bit
Reset States: 
Default = xxxx
POR/BOR = x
All Other Resets = u
ValueDescription
1 dyN is gated into g4
0 dyN is not gated into g4