26.8.8 CLCxGLS1

CLCx Gate2 Logic Select Register
Name: CLCxGLS1
Address: 0xE2E,0xE38,0xE42,0xE4C,0xE56,0xE60,0xE6A,0xE74

Bit 76543210 
 G2D4TG2D4NG2D3TG2D3NG2D2TG2D2NG2D1TG2D1N 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset xxxxxxxx 

Bits 1, 3, 5, 7 – G2DyT

dyT: Gate2 Data ‘y’ True (non-inverted) bit
Reset States: 
Default = xxxx
POR/BOR = x
All Other Resets = u
ValueDescription
1 dyT is gated into g2
0 dyT is not gated into g2

Bits 0, 2, 4, 6 – G2DyN

dyN: Gate2 Data ‘y’ Negated (inverted) bit
Reset States: 
Default = xxxx
POR/BOR = x
All Other Resets = u
ValueDescription
1 dyN is gated into g2
0 dyN is not gated into g2