26.8.8 CLCxGLS1
| Name: | CLCxGLS1 |
| Address: | 0xE2E,0xE38,0xE42,0xE4C,0xE56,0xE60,0xE6A,0xE74 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| G2D4T | G2D4N | G2D3T | G2D3N | G2D2T | G2D2N | G2D1T | G2D1N | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | x | x | x | x | x | x | x | x |
Bits 1, 3, 5, 7 – G2DyT
| Reset States: |
|
| Value | Description |
|---|---|
1 |
dyT is gated into g2 |
0 |
dyT is not gated into g2 |
Bits 0, 2, 4, 6 – G2DyN
| Reset States: |
|
| Value | Description |
|---|---|
1 |
dyN is gated into g2 |
0 |
dyN is not gated into g2 |