26.8.3 CLCxSEL0
| Name: | CLCxSEL0 |
| Address: | 0xE29,0xE33,0xE3D,0xE47,0xE51,0xE5B,0xE65,0xE6F |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| D1S[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | x | x | x | x | x | x | |||
Bits 5:0 – D1S[5:0]
| Reset States: |
|
| Value | Description |
|---|---|
| n | Refer to CLC Input Sources for input selections |