26.8.7 CLCxGLS0
| Name: | CLCxGLS0 |
| Address: | 0xE2D,0xE37,0xE41,0xE4B,0xE55,0xE5F,0xE69,0xE73 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| G1D4T | G1D4N | G1D3T | G1D3N | G1D2T | G1D2N | G1D1T | G1D1N | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | x | x | x | x | x | x | x | x |
Bits 1, 3, 5, 7 – G1DyT
| Reset States: |
|
| Value | Description |
|---|---|
1 |
dyT is gated into g1 |
0 |
dyT is not gated into g1 |
Bits 0, 2, 4, 6 – G1DyN
| Reset States: |
|
| Value | Description |
|---|---|
1 |
dyN is gated into g1 |
0 |
dyN is not gated into g1 |