26.8.7 CLCxGLS0

CLCx Gate1 Logic Select Register
Name: CLCxGLS0
Address: 0xE2D,0xE37,0xE41,0xE4B,0xE55,0xE5F,0xE69,0xE73

Bit 76543210 
 G1D4TG1D4NG1D3TG1D3NG1D2TG1D2NG1D1TG1D1N 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset xxxxxxxx 

Bits 1, 3, 5, 7 – G1DyT

dyT: Gate1 Data ‘y’ True (non-inverted) bit
Reset States: 
Default = xxxx
POR/BOR = x
All Other Resets = u
ValueDescription
1 dyT is gated into g1
0 dyT is not gated into g1

Bits 0, 2, 4, 6 – G1DyN

dyN: Gate1 Data ‘y’ Negated (inverted) bit
Reset States: 
Default = xxxx
POR/BOR = x
All Other Resets = u
ValueDescription
1 dyN is gated into g1
0 dyN is not gated into g1