26.8.5 CLCxSEL2
| Name: | CLCxSEL2 |
| Address: | 0xE2B,0xE35,0xE3F,0xE49,0xE53,0xE5D,0xE67,0xE71 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| D3S[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | x | x | x | x | x | x | |||
Bits 5:0 – D3S[5:0]
| Reset States: |
|
| Value | Description |
|---|---|
| n | Refer to CLC Input Sources for input selections |