26.8.2 CLCxPOL
| Name: | CLCxPOL |
| Address: | 0xE28,0xE32,0xE3C,0xE46,0xE50,0xE5A,0xE64,0xE6E |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| POL | G4POL | G3POL | G2POL | G1POL | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | x | x | x | x |
Bit 7 – POL
| Value | Description |
|---|---|
1 |
The output of the logic cell is inverted |
0 |
The output of the logic cell is not inverted |
Bits 0, 1, 2, 3 – GyPOL
| Reset States: |
|
| Value | Description |
|---|---|
1 |
The gate output is inverted when applied to the logic cell |
0 |
The output of the gate is not inverted |