26.8.4 CLCxSEL1
| Name: | CLCxSEL1 |
| Address: | 0xE2A,0xE34,0xE3E,0xE48,0xE52,0xE5C,0xE66,0xE70 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| D2S[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | x | x | x | x | x | x | |||
Bits 5:0 – D2S[5:0]
| Reset States: |
|
| Value | Description |
|---|---|
| n | Refer to CLC Input Sources for input selections |