26.8.9 CLCxGLS2
| Name: | CLCxGLS2 |
| Address: | 0xE2F,0xE39,0xE43,0xE4D,0xE57,0xE61,0xE6B,0xE75 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| G3D4T | G3D4N | G3D3T | G3D3N | G3D2T | G3D2N | G3D1T | G3D1N | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | x | x | x | x | x | x | x | x |
Bits 1, 3, 5, 7 – G3DyT
| Reset States: |
|
| Value | Description |
|---|---|
1 |
dyT is gated into g3 |
0 |
dyT is not gated into g3 |
Bits 0, 2, 4, 6 – G3DyN
| Reset States: |
|
| Value | Description |
|---|---|
1 |
dyN is gated into g3 |
0 |
dyN is not gated into g3 |