Directed CCC Transfer Targeted to Multiple Targets

Each transfer command initiates a directed CCC transfer to only one Target since it consists of only one DEV_INDX. If the requirement is to transfer the directed CCC command to multiple devices, then you must pipeline the multiple transfer commands in the I3CxCMDQUE with TOC bits set to zero and with the different DEV_INDX fields pointing to multiple targets. The Controller decodes the pipelined ‘Transfer command’ during the transfer of directed CCC transfer and decides the next transfer based on the following:

• If the current command and the pipelined command have the same Directed CCC, then the Controller targets the next Target without ending the CCC command.
• If the current command and the pipelined command are not the same Directed CCC, then the Controller ends the CCC command and starts issuing the next transfer as indicated by the pipelined transfer command.

The application can set the ROC bit to ‘0’ for the subsequent directed CCC commands and enable the ROC bit in the last CCC command if the directed CCC transfer is targeted to multiple devices to avoid unnecessary responses.

The Controller halts in case of the following conditions:

• Receiving a NACK for the address header of the directed CCC transfer (It means no I³C device on the bus).
• Receiving a NACK for the Target address of the directed CCC transfer.

The Controller updates the ‘ERR_STS’ field with appropriate error information in the response status (I3CxRESPQUE), halts the Controller, and returns control to the application to resume the operation of the Controller by writing ‘1’ to the I3CxCTRL [RESUME] bit.