10.4.22 Interrupt Enable Register 2
| Name: | IEC2 |
| Offset: | 0xC8 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| I2C2TXIE | I2C2RXIE | I2C2IE | I2C2EIE | I2C1TXIE | |||||
| Access | R | R | R/W | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| I2C1RXIE | I2C1IE | I2C1EIE | CMP4IE | CMP3IE | CMP2IE | CMP1IE | DMA3IE | ||
| Access | R | R | R | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DMA2IE | DMA1IE | DMA0IE | SPI3EIE | SPI3TXIE | |||||
| Access | R/W | R/W | R/W | R/W | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SPI3RXIE | SPI2EIE | SPI2TXIE | SPI2RXIE | SPI1EIE | SPI1TXIE | SPI1RXIE | |||
| Access | R | R/W | R/W | R | R/W | R/W | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 28 – I2C2TXIE I2C2 Transmit Interrupt Enable Flag bit
| Value | Description |
|---|---|
| 1 | Interrupt has occurred. |
| 0 | Interrupt event has not occurred. |
Bit 27 – I2C2RXIE I2C2 Receive Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt has occurred. |
| 0 | Interrupt event has not occurred. |
Bit 26 – I2C2IE I2C2 Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt has occurred. |
0 |
Interrupt has not occurred. |
Bit 25 – I2C2EIE I2C2 Error Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt has occurred. |
| 0 | Interrupt event has not occurred. |
Bit 24 – I2C1TXIE I2C1 Transmit Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt has occurred. |
| 0 | Interrupt event has not occurred. |
Bit 23 – I2C1RXIE I2C1 Receive Interrupt Enable Flag bit
| Value | Description |
|---|---|
| 1 | Interrupt has occurred. |
| 0 | Interrupt event has not occurred. |
Bit 22 – I2C1IE I2C1 Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt has occurred. |
| 0 | Interrupt event has not occurred. |
Bit 21 – I2C1EIE I2C1 Error Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt has occurred. |
| 0 | Interrupt event has not occurred. |
Bit 20 – CMP4IE Comparator 4 Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt has occurred. |
0 |
Interrupt has not occurred. |
Bit 19 – CMP3IE Comparator 3 Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt has occurred. |
0 |
Interrupt has not occurred. |
Bit 18 – CMP2IE Comparator 2 Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt has occurred. |
0 |
Interrupt has not occurred. |
Bit 17 – CMP1IE Comparator 1 Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt has occurred. |
0 |
Interrupt has not occurred. |
Bit 16 – DMA3IE Direct Memory Access 3 Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt has occurred. |
0 |
Interrupt has not occurred. |
Bit 15 – DMA2IE Direct Memory Access 2 Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt has occurred. |
0 |
Interrupt has not occurred. |
Bit 14 – DMA1IE Direct Memory Access 1 Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt has occurred. |
0 |
Interrupt has not occurred. |
Bit 13 – DMA0IE Direct Memory Access 0 Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt has occurred. |
0 |
Interrupt has not occurred. |
Bit 9 – SPI3EIE SPI3 Error Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt has occurred. |
0 |
Interrupt has not occurred. |
Bit 8 – SPI3TXIE SPI3 Transmit Interrupt Enable Flag bit
| Value | Description |
|---|---|
| 1 | Interrupt has occurred. |
| 0 | Interrupt event has not occurred. |
Bit 7 – SPI3RXIE SPI3 Receive Interrupt Enable Flag bit
| Value | Description |
|---|---|
| 1 | Interrupt has occurred. |
| 0 | Interrupt event has not occurred. |
Bit 6 – SPI2EIE SPI2 Error Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt has occurred. |
0 |
Interrupt has not occurred. |
Bit 5 – SPI2TXIE SPI2 Transmit Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt has occurred. |
0 |
Interrupt has not occurred. |
Bit 4 – SPI2RXIE SPI2 Receive Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt has occurred. |
| 0 | Interrupt event has not occurred. |
Bit 3 – SPI1EIE SPI1 General Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt has occurred. |
0 |
Interrupt has not occurred. |
Bit 2 – SPI1TXIE SPI1 Transmit Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Interrupt has occurred. |
0 |
Interrupt has not occurred. |
Bit 1 – SPI1RXIE SPI1 Receive Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt has occurred. |
| 0 | Interrupt event has not occurred. |