Virtual Target Read Transfers

The Target mode supports simultaneous read transfers by providing multiple Extended Commands and their related Transmit Buffers. Each extended command is mapped to its own extended Transmit Buffer to hold the data to be returned for the incoming private read or vendor-specific directed read CCCs.

After programming, the extended command registers are used by the Target to match the incoming read transfer from the Controller and respond accordingly. The data structure of the Extended Command is documented in Table 24-30.

The data transmission for a read transfer is initiated by issuing a TX transfer command. The TX transfer command can be issued by writing to the extended command registers pair (I3CxEXTCMDy_2, I3CxEXTCMDy). The command is considered valid after I3CxEXTCMDy.VALID is written to '1'.

The Target responds to a vendor-specific directed read address with ACK when the following conditions are met:

• Read transfer type and Vendor Specific received from the Controller is matched with the programmed values in one of the I3CxEXTCMDy2 and I3CxEXTCMDy registers:
  • ADDR_OFFSET: Transfer matches only with the dynamic/static address that is assigned to the respective Virtual Target.
  • CCC: Selected if a private read or vendor-specific directed read is matched.
  • CCC_HDR_HEADER
    • If CCC == 0 and CCC_HDR_HEADER == 0x00, it matches only SDR Private Read.
    • If CCC == 0 and CCC_HDR_HEADER != 0x00, it matches only HDR Private Read that have cmd_code equal to CCC_HDR_HEADER.
    • If CCC == 1, then it matches the CCC code of the incoming Vendor Specific Read CCC.
  • DEFINING_BYTE: If CCC == 1, then it matches the Defining Byte of the incoming Vendor Specific Read CCC. CCCs that have DEFINING_BYTE == 0x00 also match the CCC without a defining byte.
• The extended TX FIFO corresponds to the programmed and matched I3CxEXTCMDy and is non-empty.

To determine under which condition the NACK occurred, the Shared Peripheral Logic provides further information as follows:

• An additional interrupt, I3CxINTSTA [READREQSTA], is asserted when there is no valid command in the Command Queue.
• The I3CxCLTCCCSTAT [DATNTRDY] bit is set when the Extended TX FIFO corresponding to the programmed and matched I3CxEXTCMDy is empty.

Once the read address is acknowledged with ACK (accepted), the Target expects the application to provide enough data in the Extended TX FIFO to avoid underrun conditions. It is recommended to program enough data in the corresponding I3CxEXTTXDATy before programming the command in its equivalent I3CxEXTCMDy register.

The data length of the read transfer can be programmed with infinite data length by setting the I3CxEXTCMDy.FINITE_DL field to a 1'b0 value. Setting this field to 1'b1 represents a fixed data length read transfer with the length defined by the I3CxEXTCMDy.DATA_LENGTH.

When finite data length is configured, if the Controller tries to read less data than configured in the command, the early termination error is asserted. Only the Target ends the transfer.

When infinite data length is used, the Target ends the transfer when the transmit FIFO is empty. If the Controller ends the transfer, then the early termination error is asserted. The data length transmitted by the Target is always a multiple of four bytes.

If infinite length transfer is configured, then the Extended TX FIFO empty is considered the transfer end.

Once the TX Command is programmed in the I3CxEXTCMDy registers, the command is valid for only one read transfer. You are expected to program the I3CxEXTCMDy registers and I3CxEXTTXDATy again for the next read transfer after reading the response for the previously programmed command.

If the data length of the read transfer is more than the configured Extended FIFO buffer depth, the application is expected to monitor whether half the space is available through I3CxEXTyzBSTA registers and program the subsequent data to be transmitted by the Target.

You can program up to four TX commands at a time to respond to the incoming read transfers.

When a read transfer ends, the corresponding I3CxEXTCMDy.[VALID] bit is cleared by the hardware. At the same time, the corresponding I3CxECMDVLDSTA[CMDyVLD] bit is set and the I3C1INTSTA [EXTCMDSTA] is set. I3C1INTSTA [EXTCMDSTA] is cleared after a read from the I3CxECMDVLDSTA register.

The error status for the finished command is read from I3CxEXTCMDy [ERR_STATUS].

As read transfers are pre-agreed transfers between the Controller and Target, the Target application is expected to program the Extended Transmit buffers with the exact amount of data that can be processed by the Controller. If the Controller terminates the read transfer early, the Extended Transmit buffer of the corresponding command should be flushed by the Target application through the I3CxETXQRSTCON register to continue with programming new TX command data.