The DMTHOLDREG register is
initialized to ‘0’ on Reset, and is only loaded when the
DMTCNTL and DMTCNTH registers are read.
Name:
DMTHOLDREG(1)
Offset:
0x070
Bit
15
14
13
12
11
10
9
8
UPRCNT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
UPRCNT[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 15:0 – UPRCNT[15:0] DMTCNTH Register
Value When DMTCNTL and DMTCNTH Were Last Read bits
DS70005633B
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