16.1.2 SPIx Control Register 1 High

Note:

AUDEN can only be written when the SPIEN bit = 0.
AUDMONO can only be written when the SPIEN bit = 0 and is only valid for AUDEN = 1.
URDTEN is only valid when IGNTUR = 1.
The AUDMOD[1:0] bits can only be written when the SPIEN bit = 0 and are only valid when AUDEN = 1. When NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.

Name:	SPIxCON1H
Offset:	0x2AE, 0x2CA


Bit	15	14	13	12	11	10	9	8
	AUDEN	SPISGNEXT	IGNROV	IGNTUR	AUDMONO	URDTEN	AUDMOD[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	FRMEN	FRMSYNC	FRMPOL	MSSEN	FRMSYPW	FRMCNT[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 15 – AUDEN Audio Codec Support Enable bit⁽¹⁾

Value	Description
`1`	Audio protocol is enabled; MSTEN controls the direction of both SCKx and frame (a.k.a. LRC), and this module functions as if FRMEN = `1`, FRMSYNC = MSTEN, FRMCNT[2:0] = `001` and SMP = `0`, regardless of their actual values.
`0`	Audio protocol is disabled.

Bit 14 – SPISGNEXT SPIx Sign-Extend RX FIFO Read Data Enable bit

Value	Description
`1`	Data from RX FIFO are sign-extended.
`0`	Data from RX FIFO are not sign-extended.

Bit 13 – IGNROV Ignore Receive Overflow bit

Value	Description
`1`	A Receive Overflow (ROV) is NOT a critical error; during ROV, data in the FIFO are not overwritten by the received data.
`0`	An ROV is a critical error that stops SPI operation.

Bit 12 – IGNTUR Ignore Transmit Underrun bit

Value	Description
`1`	A Transmit Underrun (TUR) is NOT a critical error and data indicated by URDTEN are transmitted until the SPIxTXB is not empty.
`0`	A TUR is a critical error that stops SPI operation.

Bit 11 – AUDMONO Audio Data Format Transmit bit⁽²⁾

Value	Description
`1`	Audio data are mono (i.e., each data word is transmitted on both left and right channels).
`0`	Audio data are stereo.

Bit 10 – URDTEN Transmit Underrun Data Enable bit⁽³⁾

Value	Description
`1`	Transmits data out of SPIxURDT register during Transmit Underrun conditions.
`0`	Transmits the last received data during Transmit Underrun conditions.

Bits 9:8 – AUDMOD[1:0] Audio Protocol Mode Selection bits⁽⁴⁾

Value	Description
`11`	PCM/DSP mode
`10`	Right Justified mode: This module functions as if SPIFE = `1`, regardless of its actual value.
`01`	Left Justified mode: This module functions as if SPIFE = `1`, regardless of its actual value.
`00`	I²S mode: This module functions as if SPIFE = `0`, regardless of its actual value.

Bit 7 – FRMEN Framed SPIx Support bit

Value	Description
`1`	Framed SPIx support is enabled (SSx pin is used as the FSYNC input/output).
`0`	Framed SPIx support is disabled.

Bit 6 – FRMSYNC Frame Sync Pulse Direction Control bit

Value	Description
`1`	Frame Sync pulse input (Client).
`0`	Frame Sync pulse output (Host).

Bit 5 – FRMPOL Frame Sync/Client Select Polarity bit

Value	Description
`1`	Frame Sync pulse/Client select is active-high.
`0`	Frame Sync pulse/Client select is active-low.

Bit 4 – MSSEN Host Mode Client Select Enable bit

Value	Description
`1`	SPIx Client select support is enabled with polarity determined by FRMPOL (SSx pin is automatically driven during transmission in Host mode).
`0`	Client select SPIx support is disabled (SSx pin will be controlled by port I/O).

Bit 3 – FRMSYPW Frame Sync Pulse-Width bit

Value	Description
`1`	Frame Sync pulse is one serial word length wide (as defined by MODE[32,16]/WLENGTH[4:0]).
`0`	Frame Sync pulse is one clock (SCKx) wide.

Bits 2:0 – FRMCNT[2:0] Frame Sync Pulse Counter bits

Controls the number of serial words transmitted per Sync pulse.

Value	Description
`111`	Reserved
`110`	Reserved
`101`	Generates a Frame Sync pulse every 32 serial words.
`100`	Generates a Frame Sync pulse every 16 serial words.
`011`	Generates a Frame Sync pulse every 8 serial words.
`010`	Generates a Frame Sync pulse every 4 serial words.
`001`	Generates a Frame Sync pulse every 2 serial words (value used by audio protocols).
`000`	Generates a Frame Sync pulse each serial word.

DS70005633B

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