3.7 DSP Engine
The DSP engine consists of a high-speed 17-bit x 17-bit multiplier, a 40-bit barrel shifter and a 40-bit adder/subtracter (with two target accumulators, round and saturation logic).
The DSP engine can also perform inherent accumulator-to-accumulator operations that
require no additional data. These instructions are ADD,
SUB, NEG, MIN, and
MAX.
The DSP engine has options selected through bits in the CPU Core Control register (CORCON), as listed below:
- Fractional or integer DSP multiply (IF)
- Signed, unsigned or mixed-sign DSP multiply (USx)
- Conventional or convergent rounding (RND)
- Automatic saturation on/off for ACCA (SATA)
- Automatic saturation on/off for ACCB (SATB)
- Automatic saturation on/off for writes to data memory (SATDW)
- Accumulator Saturation mode selection (ACCSAT)
| Instruction | Algebraic Operation | ACC Write-Back |
|---|---|---|
CLR | A = 0 | Yes |
ED | A = (x – y)2 | No |
EDAC | A = A + (x – y)2 | No |
MAC | A = A + (x • y) | Yes |
MAC | A = A + x2 | No |
MOVSAC | No change in A | Yes |
MPY | A = x • y | No |
MPY | A = x2 | No |
MPY.N | A = – x • y | No |
MSC | A = A – x • y | Yes |