30.5.1 Control A
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | Configuration Change Protection (when enabled by CCP bit in CTRLA) |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CCP | LOCK | MODE | ENABLE | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – CCP SWDT CCP Mode
This bit enables CCP protection of most SWDT registers. It can be written only
when the LOCK bit is ‘0’.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | SWDT registers are not CCP-Protected |
| 0x1 | ENABLE | SWDT registers are CCP-Protected |
Bit 2 – LOCK SWDT Register Lock
This bit write-protects many of the registers in the SWDT and enables CCP
protection of several other SWDT registers. After it is written to
‘1’, it cannot be changed back to ‘0’.
| Value | Name | Description |
|---|---|---|
| 0x0 | UNLOCKED | SWDT registers are not Lock Protected |
| 0x1 | LOCKED | SWDT registers are Lock Protected |
Bit 1 – MODE SWDT Mode
This bit selects the operation mode of the SWDT. It can be written only when the
LOCK bit is ‘0’.
| Value | Name | Description |
|---|---|---|
| 0x0 | CLOCK | SWDT counts clock cycles |
| 0x1 | INSTRUCTION | SWDT counts executed instructions |
Bit 0 – ENABLE Enable SWDT
Writing this bit to ‘1’ enables the SWDT. This bit can be
written to ‘1’ even when the LOCK bit is ‘1’.
Once written to ‘1’ , only a reset can clear this bit.