30.5.3 Interrupt Control
| Name: | INTCTRL |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Property: | Configuration Change Protection (when enabled by CCP bit in CTRLA) |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERROR | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 3 – ERROR SWDT Error has occurred
Writing a ‘1’ to this bit enables the interrupt. This register
is writable only when the LOCK bit in the CTRLA register is
‘0’.