16.6.3 Control C
| Name: | CTRLC |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Property: | Configuration Change Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ECCALL1[1:0] | BOOTROWWP | UROWWP | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 7:6 – ECCALL1[1:0] Erased Flash ECC Check
This bit field configures the ECC-check operation when all ‘1’s are read from Flash.
In an erased Flash, all bits will read as ‘1’ for both the data
and ECC bits. Since the address is baked into the ECC calculation, reading a
random word from an erased Flash will usually result in an ECC error, which may
be problematic when prefetching one address past the last valid Flash
instruction or using the Flash to emulate EEPROM or disk.
| Value | Name | Description |
|---|---|---|
| 0x0 | CHECKALL | An ECC
check on all Flash words, including those read as all
‘1’s |
| 0x1 | DISALL | Disregard the ECC check on Flash words read as ‘1’s from
the entire Flash |
| 0x2 | DISAPPDATA | Disregard the ECC check on Flash words read as ‘1’s from
the APPDATA section or USER row |
| 0x3 | DISAPPDATAEE | Disregard the ECC check on EEPROM bytes and Flash words read as
‘1’s from the APPDATA, USERROW, or BOOTROW
sections |
Bit 1 – BOOTROWWP Boot Row Write Protect
This bit is cleared by a Reset.
This bit is set by writing a '1' to it.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ will enable the Boot Row Write Protect.
| Value | Description |
|---|---|
| 0x0 | Boot Row Updates disabled |
| 0x1 | Boot Row Updates enabled |
Bit 0 – UROWWP User Row Write Protect
This bit is cleared by a Reset.
This bit is set by writing a '1' to it.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will enable User Write Row
Protect.