16.6.6 Interrupt Flags A
| Name: | INTFLAGSA |
| Offset: | 0x05 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EEREADY | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – EEREADY EEREADY Interrupt Flag
This flag is cleared by writing a ‘1’ to it, or when the EEPROM
is busy
This flag is set when the EEPROM is ready to receive commands.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the EEREADY interrupt
flag.
Note: This flag is set as soon as the EEPROM is ready after a
Reset.