16.6.5 Interrupt Control A
| Name: | INTCTRLA |
| Offset: | 0x04 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EEREADY | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – EEREADY EEPROM Ready Interrupt
This bit controls whether the EEPROM Ready interrupt is enabled or not.
Note: The interrupt must not be enabled before triggering an
EEPROM write/erase operation, as the EEREADY bit will not be cleared before this
command is issued. Disable the interrupt in the interrupt handler.
| Value | Description |
|---|---|
| 0 | EEPROM Ready interrupt is disabled |
| 1 | EEPROM Ready interrupt is enabled |