16.6.10 Address
Continuously updated with last accessed NVM address. In the event of an ECC error, its contents are frozen and will remain like this as long as any of the ECC flags in INTFLAGSB are set. Therefore, in the case of multiple sequential ECC errors, the register will contain the address of the first error.
The NVMCTRL.ADDR0, NVMCTRL.ADDR1, NVMCTRL.ADDR2 and NVMCTRL.ADDR3 represent the 32-bit value NVMCTRL.ADDR register.
The low byte [7:0] (suffix 0) is accessible at the original offset.
The high byte [15:8] (suffix 1) can be accessed at offset
+0x01.
The extended byte [23:16] (suffix 2) can be accessed at offset
+0x02.
The byte [31:24] (suffix 3) can be accessed at offset +0x03, but it
never contains any data.
| Name: | ADDR |
| Offset: | 0x0C |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ADDR[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ADDR[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADDR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |