16.6.4 Control D
| Name: | CTRLD |
| Offset: | 0x03 |
| Reset: | 0x00 |
| Property: | Configuration Change Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COMP | PARITYD | PARITYI | ECC2 | ECC1 | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – COMP Inject ECC Comparator Mismatch Error
This bit is cleared after injecting an error.
This bit is set by writing a '1' to it.
Writing a ‘1’ to this bit will inject an ECC comparator mismatch
error on the next NVM fetch or data read.
Bit 6 – PARITYD Inject Parity Error on Data Read
This bit is cleared after after injecting an error.
This bit is set by writing a '1' to it.
Writing a ‘1’ to this bit will inject a parity error in the data
returned from the next Flash or EEPROM data read (using LD or
LPM).
Bit 5 – PARITYI Inject Parity Error on Instruction Fetch
This bit is cleared after injecting an error.
This bit is set by writing a '1' to it.
Writing a ‘1’ to this bit will inject a parity error in the next instruction fetched.
Bit 1 – ECC2 Inject 2-bit ECC Error
This bit is cleared after injecting an error.
This bit is set by writing a '1' to it.
Writing a ‘1’ to this bit will inject a 2-bit ECC error on the next NVM data read (i.e., LD or
LPM). Error is injected into LSb and Global Parity bit.
Bit 0 – ECC1 Inject 1-bit ECC Error
This bit is cleared after injecting an error.
This bit is set by writing a '1' to it.
Writing a ‘1’ to this bit will inject 1-bit ECC error on the next NVM data read (i.e., LD or
LPM). Error is injected into LSb.