16.6.7 Interrupt Flags B
| Name: | INTFLAGSB |
| Offset: | 0x06 |
| Reset: | 0x00 |
| Property: | Configuration Change Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COMP | PARITYD | PARITYA | PARITYC | EECC2 | EECC1 | FECC2 | FECC1 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – COMP Comparator Mismatch Error Interrupt Flag
This flag is cleared by writing a ‘1’ to it.
Set when a mismatch between the duplicated ECC checkers is detected. This bit is routed to ERRCTRL.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Comparator Mismatch
Error interrupt flag.
Bit 6 – PARITYD Parity Data Error Interrupt Flag
This flag is cleared by writing a ‘1’ to it.
Set when a parity error on data to be written to NVM is detected. A bus error is returned to the bus initiator when this bit becomes set. This bit is routed to ERRCTRL.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Parity Data Error
interrupt flag.
Bit 5 – PARITYA Parity Address Error Interrupt Flag
This flag is cleared by writing a ‘1’ to it.
Set when a parity error on an address to be read or written is detected. A bus error is returned to the bus initiator when this bit becomes set. This bit is routed to ERRCTRL.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Parity Address Error
interrupt flag.
Bit 4 – PARITYC Parity Control Error Interrupt Flag
This flag is cleared by writing a ‘1’ to it.
Set when a parity error on bus control signals is detected. A bus error is returned to the bus initiator when this bit becomes set. This bit is routed to ERRCTRL.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Parity Control Error
interrupt flag.
Bit 3 – EECC2 EEPROM ECC Multi-bit Error Detected Interrupt Flag
This flag is cleared by writing a ‘1’ to it.
This flag is set when a 2-bit (or more) uncorrectable error or an error in the address part is detected. A bus error is returned to the bus initiator when this bit becomes set. This bit is routed to ERRCTRL.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the EEPROM ECC Multi-bit
Error Detected interrupt flag.
Bit 2 – EECC1 EEPROM ECC 1-bit Error Detected Interrupt Flag
This flag is cleared by writing a ‘1’ to it.
This flag is set when a 1-bit correctable error in the data part is detected. This bit is routed to ERRCTRL.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the EEPROM ECC 1-bit Error
Detected interrupt flag.
Bit 1 – FECC2 Flash ECC Multi-bit Error Detected Interrupt Flag
This flag is cleared by writing a ‘1’ to it.
This flag is set when a 2-bit (or more) uncorrectable error or an error in the address part is detected. A bus error is returned to the bus initiator when this bit becomes set. This bit is routed to ERRCTRL.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Flash ECC Multi-bit
Error Detected interrupt flag.
Bit 0 – FECC1 Flash ECC 1-bit Error Detected Interrupt Flag
This flag is cleared by writing a ‘1’ to it.
This flag is set when a 1-bit correctable error in the data part is detected. This bit is routed to ERRCTRL.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit will clear the Flash ECC 1-bit Error
Detected interrupt flag.