16.6.11 ECC Parity
| Name: | PARITY |
| Offset: | 0x10 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PARITY[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – PARITY[7:0] Flash Error Parity
This bit field contains the erroneous ECC parity bits read from the memory. In the event of an ECC error, its contents are frozen and will remain like this as long as any of the ECC flags in INTFLAGSB are set. Therefore, in the case of multiple sequential ECC errors, the register will contain the data for the first error.
This register is only updated by ECC errors from NVM (Fetch, Flash data or EEPROM data). This register is reset by Power-on Reset (POR) only.