18.5.7 Main Clock Timebase
Attempting to write to this register without following the appropriate CCP unlock sequence will return a bus error.
| Name: | MCLKTIMEBASE |
| Offset: | 0x06 |
| Reset: | 0x00 |
| Property: | Configuration Change Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TIMEBASE[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 4:0 – TIMEBASE[4:0] Timebase
This bit field selects the number of CLK_PER cycles to get a period equal to or larger than 1 μs, used for timing internal delays such as ADC start-up time.