18.5.8 Main Clock Clock Failure Detect n Control A
Attempting to write to this register without following the appropriate CCP unlock sequence will return a bus error.
| Name: | MCLKCFDnCTRLA |
| Offset: | 0x08 + n*0x01 [n=0..1] |
| Reset: | 0x00 |
| Property: | Configuration Change Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CFDSRC[2:0] | CFDREF[1:0] | CFDEN | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 5:3 – CFDSRC[2:0] CFD Source
Selects the clock to monitor with the CFD channel.
| Value | Name | Description |
|---|---|---|
0x0 | MCLK | Main Clock |
0x1 | OSCHF | High frequency internal oscillator |
0x2 | OSC32K | 32.768 kHz internal oscillator |
0x3 | XOSCHF | High frequency external oscillator |
0x4 | XOSC32K | 32.768 kHz external oscillator |
0x5-0x6 | - | Reserved |
0x7 | EVSYS | Event system channel input |
Bits 2:1 – CFDREF[1:0] Clock Failure Detect Reference
Reference clock for CFD channel.
| Value | Name | Description |
|---|---|---|
0x0 | OSC32K | 32.768 kHz internal oscillator |
0x1 | ONEDIV32 | 1 MHz from OSCHF divided by 32 |
0x2 | XOSC32K | 32.768 kHz external crystal oscillator |
| Other | - | Reserved |
Bit 0 – CFDEN Clock Failure Detect Enable
Enable CFD channel.
| Value | Name | Description |
|---|---|---|
0x0 | DISABLED | CFD disabled |
0x1 | ENABLED | CFD enabled |