18.5.4 Main Clock Interrupt Control
Attempting to write to this register without following the appropriate CCP unlock sequence will return a bus error.
| Name: | MCLKINTCTRL |
| Offset: | 0x03 |
| Reset: | 0x00 |
| Property: | Configuration Change Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CFMD1 | CFMD0 | CFM1 | CFM0 | CFD1 | CFD0 | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 5 – CFMD1 Clock Frequency Measurement Done Interrupt Enable
This bit controls whether the CFMD1 interrupt is enabled or not.
| Value | Description |
|---|---|
| 0 | The interrupt is disabled |
| 1 | The interrupt is enabled |
Bit 4 – CFMD0 Clock Frequency Measurement Done Interrupt Enable
This bit controls whether the CFMD0 interrupt is enabled or not.
| Value | Description |
|---|---|
| 0 | The interrupt is disabled |
| 1 | The interrupt is enabled |
Bit 3 – CFM1 Clock Frequency Measurement Failure Interrupt Enable
This bit controls whether the CFM1 interrupt is enabled or not.
| Value | Description |
|---|---|
| 0 | The interrupt is disabled |
| 1 | The interrupt is enabled |
Bit 2 – CFM0 Clock Frequency Measurement Failure Interrupt Enable
This bit controls whether the CFM0 interrupt is enabled or not.
| Value | Description |
|---|---|
| 0 | The interrupt is disabled |
| 1 | The interrupt is enabled |
Bit 1 – CFD1 Clock Failure Detection Interrupt Enable
This bit controls whether the CFD1 interrupt is enabled or not.
| Value | Description |
|---|---|
| 0 | The interrupt is disabled |
| 1 | The interrupt is enabled |
Bit 0 – CFD0 Clock Failure Detection Interrupt Enable
This bit controls whether the CFD0 interrupt is enabled or not.
| Value | Description |
|---|---|
| 0 | The interrupt is disabled |
| 1 | The interrupt is enabled |