The value written to the Error Severity Level (ERRLVL) bit field in the associated Error
Source Control x (ERRCTRL.ESCx) register determines the severity of each error source. The
severity levels are as follows:
Table 22-1. Severity Levels| ERRLVL bit field in ESCx | Severity | Effect |
|---|
| 00 | CRITICAL |
The system has received a CRITICAL error. - The Critical Error Detected
(CRITICAL) bit in the Status A (ERRCTRL.STATUSA) register is set
- The appropriate bit in the
Error Status Flags (ERRCTRL.ESF) register is set
On the subsequent clock edge, the ERRCTRL State (STATE) bit field in the Control A
(ERRCTRL.CTRLA) register is set to Fault State (FAULT), thereby transferring the MCU
to a safe state: - The Error Controller Reset
Request is asserted. The Error Controller Reset Flag (ECRF) in the Reset Flag
Register (RSTCTRL.RSTFR) register is set to ‘
1’. - The heartbeat is stopped
- The I/O float mechanism is
activated and will float all I/O pins
|
| 01 | RESERVED | |
| 10 | NONCRITICAL |
The system has received a NONCRITICAL error. - The Noncritical Error Detected
(NONCRITICAL) bit in the ERRCTRL.STATUSA register is set
- The appropriate bit in
ERRCTRL.ESF is set
- The STATE bit field in the
ERRCTRL.CTRLA register is set to Alarm State (ALARM), and an interrupt or NMI
request is asserted
- The I/O float mechanism is
activated and will float all I/O pins if the Float all I/O Pins (FLOAT) bit in
the Error Source Control x (ERRCTRL.ESCx) register is set.
|
| 11 | NOTIFICATION |
The system has received a NOTIFICATION error. - The Notification Error Detected
(NOTIFICATION) bit in the ERRCTRL.STATUSA register is set
- The appropriate bit in
ERRCTRL.ESF is set
- The I/O float mechanism is
activated and will float all I/O pins if the FLOAT bit in ERRCTRL.ESCx is
set.
|
