22.3.7 Heartbeat
A heartbeat signal is enabled by writing ‘1’ to the Heartbeat Enable (HEART)
bit in the Control A (ERRCTRL.CTRLA) register. A 1 kHz tap from the OSC32K is used to generate
a nominal 1 kHz heartbeat. The heartbeat is asynchronous to the ERRCTRL clock.
The heartbeat signal drives the I/O pin in an open-drain configuration, i.e., it drives hard to ground in the “low” phase but releases the driver in the “high” phase, i.e., a tri-state. An internal or external pull-up is required to pull the pin to a high level.
Once enabled, the heartbeat toggles in all ERRCTRL states except FAULT and CONFIG:
- When the ERRCTRL transitions to the FAULT state, the heartbeat is immediately disabled by tri-stating the I/O pin. This immediate release may cause the last heartbeat period on the pin to be shorter than expected.
- While the ERRCTRL is in the CONFIG state,
the heartbeat output signal is forced to a logic level low. Toggling will resume when the
CONFIG state is exited, with the following possible behaviors:
- A low spike on the heartbeat if
CONFIG mode is entered when the pin is high (due to forcing it to ‘
0’ when in CONFIG) and exited before the next toggle - Shorter or longer period if a toggle should have happened
- No effect if entering CONFIG while the heartbeat is low and exiting before the heartbeat should toggle
- A low spike on the heartbeat if
CONFIG mode is entered when the pin is high (due to forcing it to ‘
The application can explicitly signal a failure to the surrounding system by writing HEART
in ERRCTRL.CTRLA to ‘0’, causing the heartbeat to stop.