18.6.1 Control B
| Name: | CTRLB |
| Offset: | 0x0004 |
| Reset: | 0x00000004 |
| Property: | Local Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| QOS[1:0] | DCCDMALVL1 | DCCDMALVL0 | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 1 | 0 | 0 | |||||
Bits 3:2 – QOS[1:0] DSU QoS Level
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Background (no sensitive operation) |
| 0x1 | LOW | Sensitive bandwidth |
| 0x2 | MEDIUM | Sensitive latency |
| 0x3 | HIGH | Critical latency |
Bits 0, 1 – DCCDMALVLn DMA Trigger n Level
| Value | Name | Description |
|---|---|---|
| 0 | EMPTY | Trigger n rises when DCCn is read and falls when it is written |
| 1 | FULL | Trigger n rises when DCCn is written and falls when it is read |