18.6.12 CoreSight ROM Table Entry 2
| Name: | ENTRY2 |
| Offset: | 0x1008 |
| Reset: | 0x00000000 |
| Property: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ADDOFF[19:12] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ADDOFF[11:4] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ADDOFF[3:0] | |||||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FMT | EPRES | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 |
Bits 31:12 – ADDOFF[19:0] CoreSight ROM Table Address Offset
The base address of the component is specified relative to the base address of this ROM table.
Bit 1 – FMT CoreSight Rom Table Format
| Value | Description |
|---|---|
| 0 | 8-bit format |
| 1 | 32-bit format |
Bit 0 – EPRES CoreSight Entry Present
This bit is set to '
0' by hardware under the
following condition:- DAL.CPU0 == DAL0, indicating that the device is locked from debug features
| Value | Description |
|---|---|
| 0 | Entry not present |
| 1 | Entry present |