13 Direct Memory Access (DMA) Controller
The Direct Memory Access (DMA) Controller is designed to service high data throughput peripherals operating on the SFR bus, allowing them to access data memory directly and alleviating the need for CPU-intensive management. The DMA controller is organized into a parameterized number of channels to provide a seamless connection to the dsPIC33A system, where each channel intercepts the interrupt from a (selectable) peripheral module as its DMA trigger. When the peripheral asserts its interrupt output, the associated DMA channel responds by providing access to the SRAM based on its programming without any CPU intervention. Each functioning DMA channel interrupts the CPU when the DMA session is over or upon other available interrupt conditions. This increases the overall system performance in high-bandwidth demand, and it decreases dynamic power dissipation in low throughput applications.
The DMA Controller has these features:
- Eight Independent Channels
- Concurrent Operation with the CPU (No DMA Caused Wait States)
- DMA Bus Arbitration
- Four Address Modes
- Four Transfer Modes
- Ping-Pong Mode (Automatic Switch Between Two Channels After Each Block Transfer Completes)
- 8-Bit, 16-Bit or 32-Bit Word Support for Data Transfer
- 24-Bit Source and Destination Address Register for Each Channel, Dynamically Updated and Independently Reloadable
- 32-Bit Transaction Count Register, Dynamically Updated and Independently Reloadable
- Upper and Lower Address Limit Registers
- Counter Half-Full Level Interrupt
- Software Triggered Transfer
- Null Write Mode for Symmetric Buffer Operations
- Fixed Priority and Round Robin Channel Arbitration
- DMA Request for Each Channel can be Selected from Any Supported Interrupt Source
- Support for Daisy-Chaining of Channels (One Channel Triggered by Another Channel)
- Set/Clear/Invert Bit Manipulation Capability
- Pattern Match
- Bus Read/Write Error Fault Indication