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High-Performance dsPIC33A Core with Floating-Point Unit, High-Speed ADCs and High-Speed PWM
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Operating Conditions
High-Performance dsPIC33A DSP/CISC CPU
Memory Features
Security Features
High-Speed PWM
High-Speed Analog-to-Digital Converters
Peripheral Features
Analog Features
Safety Features
Functional Safety Support
Qualification
Programming and Debug Interfaces
dsPIC33AK512MPS512
Family Features
Pin Diagrams
Pinout I/O Descriptions
Terminology Cross Reference
1
Device Overview
2
Guidelines for Getting Started with Digital Signal Controllers
2.1
Basic Connection Requirements
2.2
Decoupling Capacitors
2.3
Power Sequencing
2.4
Buck Converter Guidelines and Considerations
2.5
Master Clear (
MCLR
) Pin
2.6
ICSP Pins
2.7
External Oscillator Pins
2.8
External Oscillator Layout Guidance
2.9
Oscillator Value Conditions on Device Start-up
2.10
Unused I/Os
2.11
Targeted Applications
3
CPU
3.1
Architectural Overview
3.2
Register Summary
3.3
Operation
3.4
Prefetch Branch Unit (PBU)
3.5
Performance Monitor Unit (PMU)
3.6
Floating-Point Unit (FPU) Coprocessor
4
Memory Organization
4.1
Device-Specific Information
4.2
Architectural Overview
4.3
Register Summary
4.4
BMX Operation
4.5
Application Example
5
Data Memory
5.1
Device-Specific Information
5.2
Architectural Overview
5.3
Register Summary
5.4
Operation
6
Flash Program Memory
6.1
Device-Specific Information
6.2
Register Summary
6.3
Operation
6.4
Flash Dual Partition
6.5
Application Example
7
Configuration Bits
7.1
Configuration Register Summary
7.2
Device Calibration and Identification
8
Security Module
8.1
Architectural Overview
8.2
Register Summary
8.3
Flash Memory Map
8.4
Device Locking
8.5
Flash Protection Regions
8.6
Cryptographic Accelerator
8.7
Peripheral Access Controller (PAC)
9
Resets
9.1
Architectural Overview
9.2
Register Summary
9.3
Operation
9.4
Application Example
9.5
Effects of Reset
10
Interrupt Controller
10.1
Device-Specific Information
10.2
Architectural Overview
10.3
Interrupt Vector Table
10.4
Interrupt Controller Register Summary
10.5
Operation
10.6
Interrupt Control and Status Registers
10.7
Priority
10.8
Interrupt Sequence
10.9
Non-Maskable Traps
10.10
Interrupt Operations
11
I/O Ports with Edge Detect
11.1
Device-Specific Information
11.2
Architectural Overview
11.3
Register Summary
11.4
Operation
11.5
Application Example
11.6
Interrupts
11.7
Power-Saving Modes
11.8
Effects of Various Resets
12
Oscillator Module
12.1
Device-Specific Information
12.2
Architectural Overview
12.3
Register Summary
12.4
Operation
13
Direct Memory Access (DMA) Controller
13.1
Device-Specific Information
13.2
Architectural Overview
13.3
Register Summary
13.4
Operation
13.5
Application Examples
13.6
Interrupts
13.7
Power-Saving Modes
14
CAN Flexible Data-Rate (FD) Protocol Module
14.1
Device-Specific Information
14.2
Features
14.3
CAN FD Message Frames
14.4
Register Summary
14.5
Modes of Operation
14.6
Configuration
14.7
Message Transmission
14.8
Transmit Event FIFO - TEF
14.9
Message Filtering
14.10
Message Reception
14.11
FIFO Behavior
14.12
Timestamping
14.13
Interrupts
14.14
Error Handling
15
High-Resolution PWM with Fine Edge Placement
15.1
Device-Specific Information
15.2
Architectural Overview
15.3
Registers
15.4
Operation
15.5
Application Examples
15.6
Interrupts
15.7
Power-Saving Modes
16
40 MSPS Analog-to-Digital Converter (ADC)
16.1
Device-Specific Information
16.2
ADC Architectural Overview
16.3
Register Summary
16.4
Operation
16.5
Application Examples
16.6
Effects of Reset
17
Integrated Touch Controller (ITC)
17.1
Device-Specific Information
17.2
Registers
17.3
Touch Controller Operation
17.4
Application Example
18
High-Speed Analog Comparator with Slope Compensation DAC
18.1
Device-Specific Information
18.2
Architectural Overview
18.3
Register Summary
18.4
Operation
18.5
Application Examples
19
Quadrature Encoder Interface (QEI)
19.1
Device-Specific Information
19.2
Architectural Overview
19.3
Register Summary
19.4
Operation
19.5
Application Example
19.6
Interrupts
19.7
Power-Saving Modes
20
Universal Asynchronous Receiver Transmitter (UART)
20.1
Device-Specific Information
20.2
Architectural Overview
20.3
Register Summary
20.4
Operation
20.5
Application Examples
20.6
Interrupts
20.7
Power-Saving Modes
21
Serial Peripheral Interface (SPI)
21.1
Device-Specific Information
21.2
Architectural Overview
21.3
Register Summary
21.4
Operation
21.5
Interrupts
21.6
Power-Saving and Debug Modes
22
Inter-Integrated Circuit (I
2
C)
22.1
Device-Specific Information
22.2
Architectural Overview
22.3
I2C System Overview
22.4
Register Summary
22.5
Operation
22.6
Application Examples
22.7
Interrupts
22.8
Operation in Power-Saving Modes
23
Single-Edge Nibble Transmission (SENT)
23.1
Device-Specific Information
23.2
Architectural Overview
23.3
Register Summary
23.4
Operation
23.5
Application Examples
23.6
Interrupts
23.7
Power-Saving Modes
23.8
Effects of a Reset
24
Bidirectional Serial Synchronous (BiSS) Module
24.1
Device-Specific Information
24.2
Architectural Overview
24.3
Register Summary
24.4
Operation
24.5
Application Examples
24.6
Interrupts
24.7
Power Saving Modes
24.8
Terminology
25
Timers
25.1
Device-Specific Information
25.2
Architectural Overview
25.3
Register Summary
25.4
Operation
25.5
Interrupts
25.6
Power-Saving Modes
25.7
Effects of Various Resets
26
Capture/Compare/PWM/Timer Modules (CCP)
26.1
Device-Specific Information
26.2
MCCP
26.3
Architectural Overview
26.4
Register Summary
26.5
Operation
26.6
Power-Saving Modes
26.7
Effects of a Reset
27
Configurable Logic Cell (CLC)
27.1
Device-Specific Information
27.2
Architecture
27.3
Register Summary
27.4
Operation
27.5
CLC Application Example
27.6
CLC Interrupts
27.7
Power-Saving Modes
28
Peripheral Trigger Generator (PTG)
28.1
Device-Specific Information
28.2
Architectural Overview
28.3
Register Summary
28.4
Operation
28.5
Application Examples
28.6
Interrupts
28.7
Power-Saving Modes
29
32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
29.1
Architectural Overview
29.2
Register Summary
29.3
Operation
29.4
Application Examples
29.5
Power-Saving Modes
30
Current Bias Generator (CBG)
30.1
Device-Specific Information
30.2
Architectural Overview
30.3
Current Bias Generator Control Register
Current Bias Generator Control Register
30.4
Operation
30.5
Application Examples
30.6
Interrupts
30.7
Power-Saving Modes
30.8
Effects of a Reset
31
UREF Reference Output
31.1
Device-Specific Information
31.2
UREF Control Register 1
UREF Control Register 1
32
Operational Amplifier (Op Amp)
32.1
Device-Specific Information
32.2
Architectural Overview
32.3
Op Amp Register Summary
32.4
Operations
32.5
Op Amp Application Examples
33
Watchdog Timer (WDT)
33.1
Device-Specific Information
33.2
Architectural Overview
33.3
Register Summary
33.4
Operation
33.5
Watchdog Timer Reset
33.6
Operation of Watchdog Timer in Sleep/Idle Modes
33.7
WDT Generic Trap
33.8
WDT Sample Configuration
34
Deadman Timer (DMT)
34.1
Architectural Overview
34.2
Register Summary
34.3
Operation
35
Device Power-Saving Modes
35.1
Architectural Overview
35.2
Register Summary
35.3
Operation
36
JTAG Interface
37
In-Circuit Debugger
38
Instruction Set Summary
39
Development Support
40
Electrical Characteristics
40.1
DC Characteristics
40.2
AC Characteristics and Timing Parameters
41
Packaging Information
41.1
Package Marking Information
41.2
Package Details
42
Revision History
43
Product Identification System
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature
