7.2.1 Nonvolatile Memory (NVM) Control Register

Note:

A BOR event Reset will indirectly clear WR by forcing the FSM to terminate the operation underway. The WR bit cannot be set if the operation target address held in the NVMADRx register falls within unimplemented address space.
Reset only on POR or BOR, but actual initial state of P2ACTIV visible to the user will depend upon which panel is determined to be active after Reset exit.
A BMX address error is likely due to a bad NVMSRCADR value. The same error will generate a Bus error TRAP via the interrupt controller. This will aid the software in diagnosing the issue.
WRERR bit will remain set if an attempt is made to execute (WR=1) a reserved PROGOP command. WR bit will not remain set.
“Word” is defined to be a 128-bit data value plus ECC (140 bits total). However, each word program command may consist of a sequence of fractional word programming operations.
Reserved when in Single Boot mode (DUAL_BOOTPRESENT=0).

Legend: C = Clearable bit; SO = Settable Only bit

Name:	NVMCON
Offset:	0x3000


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
				WRRE		WREC[2:0]
Access				R/W		R/W	R/W	R/W
Reset				0		0	0	0


Bit	15	14	13	12	11	10	9	8
	WR	WREN	WRERR	NVMPIDL	SFTSWAP	P2ACTIV
Access	R/SO	R/W	R/W	R/W	R/C	R
Reset	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	LOCK	DRBV			MVMOP[3:0]
Access	R/W	R/W			R/W	R/W	R/W	R/W
Reset	0	0			0	0	0	0

Bit 20 – WRRE Program/Erase Reset Event bit

Value	Description
`1`	Warm Reset request during program/erase operation
`0`	No event reported Write 0 to clear, writing 1 has no effect.

Bits 18:16 – WREC[2:0] Program/Erase Error Code bits

Value	Description
`101`	Row programming operation is not completed due to warm Reset
`100`	System bus error during a Row Program operation
011	Error reported by Flash panel control logic
010	Security access control violation
001	Invalid program/erase operation (PROGOP)
000	No error Unused codes are reserved. Read as ‘0’ if WRERR=0

Bit 15 – WR Write Control bit⁽¹⁾

Value	Description
`1`	Initiates a memory or fuse element program or erase operation.
`0`	Program or erase operation is complete and inactive.

Bit 14 – WREN Program/Erase Enable bit

Value	Description
`1`	Allows program/erase cycles.
`0`	Inhibits programming/erasing of memory or fuse elements. This bit cannot be updated if either the LOCK bit is set or the WR bit is set.

Bit 13 – WRERR Sequence Error Flag bit

Value	Description
`1`	Indicates an improper program or erase termination due to: An attempt to execute a reserved `PROGOP` command. An error detected by the Smart Write module such as Flash failures. If a BMX address error is detected during a row programming operation. This bit cannot be set by software.
`0`	Either a POR or BOR has occurred or software cleared the WRERR bit.

Bit 12 – NVMPIDL NVM Power Down in Idle Enable bit

Value	Description
`1`	Flash panels enter a Sleep mode (very low power mode) when device enters Idle mode.
`0`	Keep Flash and Fuse panels powered in Standby mode when the device enters Idle mode.

Bit 11 – SFTSWAP Soft Swap Status bit

Value Description

Value	Description
1	When Dual Boot Mode is present: Panels have been successfully swapped using the `BOOTSWP` instruction.
0	Awaiting successful panel swap using the `BOOTSWP` instruction.
	When Dual Boot Mode, `BOOTSWP` not possible: Read as ‘`0`’

When Dual Boot Mode is present:

Panels have been successfully swapped using the BOOTSWP instruction.

Awaiting successful panel swap using the BOOTSWP instruction.

When Dual Boot Mode, BOOTSWP not possible:

Read as ‘0’

Bit 10 – P2ACTIV Dual Boot Active Region Status bit⁽²⁾

Value Description

Value	Description
`1`	When Dual Boot Mode is present: Panel 2 is mapped into Active region.
`0`	Panel 1 is mapped into Active region.
	When Dual Boot Mode, BOOTSWP not possible: Read as ‘`0`’

1

When Dual Boot Mode is present:

Panel 2 is mapped into Active region.

0

Panel 1 is mapped into Active region.

When Dual Boot Mode, BOOTSWP not possible:

Read as ‘0’

Bit 7 – LOCK Lock bit

Value Description

1 Program/erase functions are disabled until after the next Reset.

Value	Description
`1`	Program/erase functions are disabled until after the next Reset.
`0`	Program/erase functions are not disabled. Write 1 to set, writing 0 has no effect.

0

Program/erase functions are not disabled.

Write 1 to set, writing 0 has no effect.

Bit 6 – DRBV Data Read Buffer Valid bit

Value Description

1 Data read buffer holds valid data.

Value	Description
`1`	Data read buffer holds valid data.
`0`	Data read buffer invalid Write 0 to clear, writing 1 has no effect.

0

Data read buffer invalid

Write 0 to clear, writing 1 has no effect.

Bits 3:0 – MVMOP[3:0] NVM Operation Select bits^(3,4,5,6)

Value	Description
0111-0101	Reserved
0100	Next WR command performs an Inactive Partition Erase operation.
0011	The next WR command will perform a memory Page Erase operation.
0010	The next WR command will perform a Row program 1 operation.
0001	The next WR command will perform a Word program 1, 3 operation (data source: NVMDATAx).
0000	Reserved