54.14.9 PDEC - Position Decoder Electrical Specifications

Figure 54-29. Position Decoder (PDEC) Timing Diagrams Counter Mode
Figure 54-30. PDEC[0]/PDEC[1] Input Characteristics
Table 54-67. Quadrature Encoder Interface Electrical Specifications (1)
AC CHARACTERISTICSStandard Operating Conditions: VDDIO=VDDANA 1.71V to 3.63V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

Param. No.SymbolCharacteristicsMin.TypMax.UnitsConditions
TP1TtPHTPCK high time2/fQEICLK+1.3 nsVDDIOx(min) -to- VDDIOx(max)
TP3TtPLTPCK low time2/fQEICLK + 0.9 ns
TP5TtPPTPCK input period4/fQEICLK+ 2.2 ns
TP7TCKEXTDLYDelay from External TxCK Clock Edge to counter Increment 4/fQEICLK+20.5ns
TP11TPDHPosition Decoder Input High Time4/fQEICLK+30.9 ns
TP13TPDLPosition Decoder Input Low Time4/fQEICLK+30.9 ns
TP15TPDINPosition Decoder Input Period8/fQEICLK+61.8 ns
TP17TPDPPosition Decoder Phase Period2/fQEICLK+15.5 ns
TP21TPDFHFilter Time to Recognize Low, with Digital Filter4/fQEICLK+20.5 ns
TP23TPDFLFilter Time to Recognize High, with Digital Filter4/fQEICLK+20.5 ns
TP24fQEICLKGCLK for PDEC 200MHz
Note:
  1. These values are based on simulation. They are not covered by production test limits or characterization.