2.9.6.1 Timing Constraints

The REF_CLK, HS_IO_CLK, HS_IO_CLK_270, and SYS_CLK clocks generated using the dedicated PLL require timing constraints for synthesis, place and route, and timing verification. To generate these timing constraints, select the Timing tab in Constraint Manager, and click Derive Constraints as shown in the following figure.

Figure 2-70. Constraint Manager—Derive Constraints Tab

When prompted, click Yes to apply the derived constraints for synthesis, place and route, and timing verification.

Important: Synthesizing the PF_DDR4 memory controller generates the “CL118” warning, which reports the generation of a latch for the apb_data_out[7:0] signal in the dq_align_dqs_optimization.v file. The issue originates from the unused COREDDR_TIP APB interface, which is not utilized. This warning does not impact the functionality of the PF_DDR4 memory controller and can be ignored by the user.