2.9.6.2 Physical Constraints

DDR memory controllers can be placed only in the pre-defined locations that are optimized for maximum performance. The maximum width of the DDR memory varies based on die/package combination and placement. For information about the DDR placement, see the respective PPATs as follows:

The DDR subsystem location is selected using the Physical Design Constraint (PDC) or the I/O Editor. Libero assigns the I/Os based on the selection of the DDR memory location. Before placing the DDR subsystem to the required I/O Bank location, the VDDI and VREF of that I/O Bank must be set to the appropriate value. In I/O Editor, the VDDI and VREF are set using the I/O Bank Settings option.

Important: Enabling Synplify soft Triple Module Redundancy (TMR) option, syn_radhardlevel on these memory controllers is not recommended. Performance impacts due to the spatial TMR of the logic can result in timing closure failures in these high performance controllers. The recommendation is to monitor the memory subsystem for signs of SEU failures during normal operation. If failure is detected, reset the subsystem.