Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The interrupt is sampled during Q1 of the instruction cycle. The actual interrupt latency then depends on the instruction that is executing at the time the interrupt is detected. See the following figures for more details.
Figure 1. Interrupt Latency
Figure 2. INT Pin Interrupt
Timing
Notes:
- 1.INTF flag is sampled here (every Q1).
- 2.Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single-cycle or a two-cycle instruction.
- 3.For minimum width of INT pulse, refer to AC specifications in the “Electrical Specifications” section.
- 4.INTF may be set any time during the Q4-Q1 cycles.