55.28 QSPI Electrical Specifications

Figure 55-12. QSPI SDR Host Mode 0,1,2,3 Module Timing Diagram

Figure 55-13. QSPI DDR Mode 0 Write Timing Diagram

Figure 55-14. QSPI DDR Mode 0 Read Timing Diagram

Table 55-40. QSPI Module Electrical Specifications ⁽¹⁾
AC CHARACTERISTICS			Standard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ T_A ≤ +85°C for Industrial Temperature
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
QSPI_1	FCLK	Serial Clock Frequency	—	—	75	MHz	Host SDR Transfer Mode 0 and 2 (BAUD.CPHA = 0), VDD=3.3V, C_LOAD=20pF(MAX)
					50		Host SDR Transfer Mode 0 and 2 (BAUD.CPHA = 0), VDD=1.8V, C_LOAD=20pF(MAX)
					50		Host SDR Transfer Mode 1 and 3 (BAUD.CPHA = 1), VDD=3.3V, C_LOAD=20pF(MAX)
					50		Host SDR Transfer Mode 1 and 3 (BAUD.CPHA = 1), VDD=1.8V, C_LOAD=20pF(MAX)
					66		Host DDR Transfer Mode 0 in Read only (BAUD.CPHA = 0, BAUD.CPOL = 0), VDD=3.3V, CLOAD=20pF(MAX)
					37.5		Host DDR Transfer Mode 0 in Read only (BAUD.CPHA = 0, BAUD.CPOL = 0), VDD=1.8V, C_LOAD=20pF(MAX)
QSPI_3	TSCKH	Serial Clock High Time	1/(2*FCLK)	—	—	ns	—
QSPI_5	TSCKL	Serial Clock Low Time	1/(2*FCLK)	—	—	ns	—
QSPI_7	TSCKR	Serial Clock Rise Time	—	—	DI_27	ns	DI_27: Refer to I/O Pin Electrical Specifications
QSPI_9	TSCKF	Serial Clock Fall Time	—	—	DI_25	ns	DI_25: Refer to I/O Pin Electrical Specifications
QSPI_19	TDIS	Data In Setup Time	4.3	—	—	ns	VDD= 3.3V Host SDR mode 0
			4.55	—	—	ns	VDD= 3.3V Host SDR mode 1
			4.17	—	—	ns	VDD= 3.3V Host SDR mode 2
			4.68	—	—	ns	VDD= 3.3V Host SDR mode 3
			4.17	—	—	ns	VDD= 3.3V Host DDR mode 0
QSPI_21	TDIH	Data In Hold Time	0	—	—	ns	VDD= 3.3V Host SDR mode 0
			0	—	—	ns	VDD= 3.3V Host SDR mode 1
			0	—	—	ns	VDD= 3.3V Host SDR mode 2
			0	—	—	ns	VDD= 3.3V Host SDR mode 3
			0	—	—	ns	VDD= 3.3V Host DDR mode 0
QSPI_23	TDOH	Data Out Hold	0	—	—	ns	—
QSPI_25	TDOV	Data Out Valid	—	—	2.37	ns	VDD=3.3V Host SDR mode 0
			—	—	2.96	ns	VDD= 3.3V Host SDR mode 1
			—	—	2.37	ns	VDD= 3.3V Host SDR mode 2
			—	—	2.73	ns	VDD= 3.3V Host SDR mode 3
			—	—	2.17	ns	VDD= 3.3V Host DDR mode 0
Note: Assumes VDD(MAX) and 20pF external load on all QSPI pins unless otherwise noted.

Table 55-41. QSPI Maximum Frequency Example ⁽¹⁾
AC CHARACTERISTICS			Standard Operating Conditions: VDD = AVDD = 1.71V to 3.63V (unless otherwise stated) Operating temperature: -40°C ≤ T_A ≤ +85°C for Industrial Temperature
QSPI Mode	CLK_QSPI2X_AHB	CLK_QSPI_AHB	Max. f_CPU	Max. QSPI Serial Clock Frequency ⁽²⁾	Conditions
SDR	X	120 MHz	120 MHz	60 MHz	BAUD.BAUD[7:0] must be greater than 0 to ensure QSPI clock frequency is as per electrical specifications provided
SDR	X	75 MHz	75 MHz	75 MHz	-
DDR	132 MHz	66 MHz	66 MHz	66 MHz	MCLK: HSDIV.DIV=0x01 MCLK: CPUDIV.DIV=0x02
Note: Examples shown do not supersede the electrical specification shown in QSPI Module Electrical Specifications table. Refer to QSPI_1 for maximum QSPI Serial Clock Frequency (FCLK) in SDR and DDR modes.

PIC32CX SG41/SG60/SG61 Family Data Sheet

55.28 QSPI Electrical Specifications