7 NVMCTRL

RDBUFWS

Setting the RDBUFWS bits = 1 stalls the FCR read access.

Workaround

The RDBUFWS bits should all be set to 0. The feature for deterministic FCR wait states is non-functional.

Affected Silicon Revisions

A1A2
X-

PRM

NVMCTRL Power Reduction mode is non-functional. The default values of NVMCTRL.CTRLB.PRM = 0x0 and NVMCTRL.CTRLB.SLP = 0x0 must be maintained for proper operation.

Workaround

None.

Affected Silicon Revisions

A1A2
XX

CRCMLEN

CRCMLEN active bits can exceed the PFM size for devices with Flash panels smaller than 8M Bytes.

Workaround

The value written to CRCMLEN should not exceed the size of the PFM.

Examples: 8M – 0x800000 | 4M – 0x400000 | 2M – 0x200000

Affected Silicon Revisions

A1A2
XX

CTRLA.ADRWS

When CTRLA.ADRWS is set to 1, reads to the same address across NVM regional boundaries can yield stale data.

Workaround

CTRLA.ADRWS should be set to 0.

Affected Silicon Revisions

A1A2
X-

CRC

FCR does not check addresses to verify they fall within a valid Flash memory region.

Workaround

Application code should make certain that configured CRC calculations do not extend beyond the valid PFM address range.

Affected Silicon Revisions

A1A2
XX

ECCCTRL

The ECC mode settings 0x10 (Dynamic Writes with Dynamic Reads but w/o Bus Error) and 0x01 (Dynamic Writes with Dynamic Reads) are not functional for all possible read/write operations.

Workaround

Do not use the ECCCTRL settings 0x10 (Dynamic Writes with Dynamic Reads but w/o Bus Error) and 0x01 (Dynamic Writes with Dynamic Reads).

Affected Silicon Revisions

A1A2
X-

DBGCTRL.DGBECC

Bus errors reported to debugger when FCR -> DBGCTRL.DBGECC = 0 (NOERR).

Workaround

None.

Affected Silicon Revisions

A1A2
XX

Fault Address Capture

The CRC in fixed read addressing mode is broken (CHCTRLBn.RAS being either 3, 4, or 5).

Workaround

None.

Affected Silicon Revisions

A1A2
XX