3 DMA
CRC
DMA Channel CRCROUT and CRCXOR settings are applied to CRC data only, and not applied on CRC Append Data.
Workaround
None.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
BYTORD
DMA.BYTORD: The DMA byte reordering settings for CHCTRLBk.BYTORD[1:0] and CHCTRLBk.WBOEN are incorrectly applied to descriptor data. The byte reordering feature is non-functional.
Workaround
None.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
Pattern Match
When using pattern match feature on a channel with CHCTRLBk.WAS set to 101 (FIXED_WORD_ADDR_INC), incorrect data may be written to the destination. This is the only setting of CHCTRLBk.WAS that exhibits this issue.
Workaround
None.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
Linked List Event System Abort
Linked list event system aborts are not supported (CHEVCTRLn.EVAUXIE = 1 and CHEVCTRLn.EVAUXACT = 11).
Workaround
None.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
SYNCBUSY.ENABLE
When the module is configured in SPI Client or I2C Client mode, SYNCBUSY.ENABLE may remain set indefinitely if the GCLK frequency is significantly slower than the APB clock. The issue is still present if Software polls the SYNCBUSY.ENABLE.
Workaround
None.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
When CRCEN = 1 Output Data is Broken
The CRC in fixed read addressing mode is broken (CHCTRLBn.RAS being either 3, 4, or 5).
Workaround
None.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
IP Header Checksum Mode
Using CRCMD = 7 (IP header checksum mode) should be avoided when RAS = 2, 3, or 5, as an incorrect checksum could be calculated.
Workaround
None.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
Event System and Pattern Match Aborts
If using pattern match (CHCTRLBn.PATEN = 1) or if the event system aborts (CHEVCTRLn.EVAUXIE = 1 and CHEVCTRLn.EVAUXACT = 00 or 11), then Channel Event Outputs cannot be used (CHEVCTRLn.EVOE must remain 0).
Workaround
None.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
Descriptor Loading
CHCTRLA.ENABLE = 1 and LLEN = 1 do not load the description.
Workaround
- If software writes LLEN = 1 and ENABLE = 0 (same write), load the next descriptor
- If software writes LLEN = 1 and ENABLE = 1 (same write), load the next descriptor
- If software writes LLEN = 0 and ENABLE = 1 (same write), the channel completes the block transfer and clears the enable. The software should not write LLEN = 1 until after this block transfer completes.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
Pattern Match
With EVOMODE = STRB_START_EVT_TRG_TO_CELL_XFER_READ and EVOE = 1, a pattern-match or Event System abort may leave the DMA event flag set, causing an unintended DMAC_EVSYS_CHn_EVT during the next block transfer.
Workaround
After detecting a pattern-match abort or event-system abort in this configuration, issue a DMA channel reset before starting the next block transfer. The channel reset clears the internal event flag.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |