16 SERCOM
LIN
- CTRLC.HDRDLY = 0x2: Where the delay between the sync and ID transmission fields is 8-bit time instead of 4-bit time
- CTRLC.HDRDLY = 0x3: Where the delay between the sync and ID transmission fields is 14-bit time instead of 4-bit time
Workaround
None.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
LIN - Two Stop Bits
Two stop bits mode (CTRLB.SBMODE = 0x1) is not supported in SERCOM USART LIN Host mode (CTRLA.FORM = 0x2) in the case where break, sync, and identifier fields are automatically transmitted when DATA is written with the identifier (CTRLB.LINCMD = 0x2). Only one stop bit mode is supported.
Workaround
None.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
SPI Host Mode
In SPI Host mode with CTRLB.MSSEN = 0, the INTFLAG.TXC flag may be asserted earlier than expected if new data is written to the DATA register close to the end of the previous byte transmission. This may cause the application to desert the Chip Select line before the SPI transfer is complete.
Workaround
- Insert a delay of at least 8 SPI clock cycles after the last DATA write before deserting the Chip Select line.
- Enable inter-character spacing by setting CTRLC.ICSPACE = 1, which inserts a one SCK cycle delay between transmitted bytes.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
SPI/I2C Client Mode
When the module is configured in SPI Client or I2C Client mode, SYNCBUSY.ENABLE may remain set indefinitely if the GCLK frequency is significantly slower than the APB clock. The issue presents even if the software polls the SYNCBUSY.ENABLE.
Workaround
None.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
I2C Host Mode
In I2C host mode, when the FIFO is enabled (CTRLC.FIFOEN = 1), the GCLK clock frequency must be higher than or equal to the APB bus clock frequency.
Workaround
None.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |