4 IxS
MCLKn
Assigning the IxS MCLKn signal to a pin through the I/O MUX does not enable the output.
Workaround
After assigning an IxS MCLKn signal to a pin, enable the output for the pin in the corresponding Data Direction register.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
FRMCNT
When FRAMECTRL.FRMCNT is set to 0x0, a frame sync pulse must be generated for each serial word (slot). Actual behavior is that one frame sync pulse is generated for every two serial words (slots) when FRAMECTRL.FRMCNT is set to 0x0.
Workaround
None.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
I8S
When operating in I8S left or right justified client mode, data from the client is not transmitted properly and is erroneous.
Workaround
Use TDM mode rather than I8S mode.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |