18 OSCCTRL
DFLL48M
When the DFLL48M is used dynamically (enabled and disabled during application run-time, on-demand, or otherwise), tuning can be corrupted when re-enabled.
Workaround
To prevent this issue, it is necessary to use a small step size (recommend DFLLMUL.STEP = 1) and to disable quick lock (DFLLCTRLB.QLDIS = 1) in case dynamic operation of the DFLL48M is required.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |
DFLL
DFLL Fails to Lock at 8 MHz in Low-Power mode under extreme conditions.
Workaround
When operating in Low-Power mode, avoid using the DFLL directly in the 8 MHz configuration. Instead, configure the DFLL for 48 MHz and divide the clock to 8 MHz, or use an alternate clock source.
Affected Silicon Revisions
| A1 | A2 | ||||
|---|---|---|---|---|---|
| X | X |